1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more specifically to an interconnect technology incorporating a low-k film, which is an interlayer insulating film of a low relative dielectric constant.
2. Description of the Related Art
As the packing density of a semiconductor device is increased, the width and thickness of interconnect layers become smaller, and the spacing between the interconnect layers becomes smaller. This increases signal delay times. A delay time is determined by a parasitic resistance R and a parasitic capacitance C of interconnects. Basically, as the interconnects become finer, both the parasitic resistance R and the parasitic capacitance C increase. The parasitic resistance R can be reduced by adopting a low-resistance material such as copper for an interconnect material (Cu interconnects). On the other hand, the parasitic capacitance C decreases as the effective dielectric constant keff of the interlayer insulating film deposited between the interconnects is reduced. In other words, the parasitic capacitance C can be reduced by the interlayer insulating film having a lower relative dielectric constant k, and therefore an interlayer insulating film having a low relative dielectric constant (k is 3.0 or less), called a low-k film, has been employed.
However, when interconnect trenches are formed in a low-k film by plasma treatment (for hardmask layer formation and RIE), a reaction occurs between oxygen utilized in the treatment and carbon. Due to this reaction, carbon escapes from the low-k film, producing a “damaged layer” on the surface of the low-k film (see, for example, Jeong-Hoon Ahn, “Integration of a low-k α-SiOC:H dielectric with Cu interconnects”, Journal of the Korean Physical Society (South Korea) Vol. 41, No. 4, October 2002, pp. 422-426; Gross, T. S., “Nanoscale observation of dielectric damage to low k MSQ interconnects”, Materials, Technology and Reliability of Advanced Interconnects—2005, Symposium (Materials Research Society Proceedings, Vol. 863) xiii+411, pp. 165-169 2005; and Bhanap. A, “Repairing process-induced damage to porous low-k ILDs by post-ash treatment”, Advanced Metallization Conference 2003 xxiii+792 pp. 519-523 2004). The damaged layer, which has a high relative dielectric constant, increases the capacitance between the interconnects. Furthermore, because the damaged layer can easily absorb moisture, the barrier metal and Cu interconnects tend to undergo oxidation, which reduces the reliability of the interconnects. In order to avoid such problems, the damaged layer is removed with a hydrofluoric acid solution after the interconnect trench formation. This wet etching treatment using the solution is performed also to remove process residues on the lower interconnect at the bottom of the via. Without this treatment, conduction defects would occur between the via and the lower interconnect.
However, the wet etching of the damaged layer proceeds more quickly than the etching of hardmask layer. For this reason, undercuts are created in the low-k film beneath the hardmask layer HM (SiO2 film in this example), as shown in FIGS. 1A and 1B (see the area [HM undercut] circled in FIG. 1B). The overhang portions formed by these undercuts lead to defects caused by insufficient embedment of interconnect metal into the interconnect trenches. Hence, the defects in the embedment may occur along the interconnect trenches as indicated by white streaks in FIG. 1C, and voids appear as indicated by blackened areas disturbing the patterns in the lower left corner of the drawing.